Product Overview
  • SONET/SDH framer/aggregator for use in channelized STS-192/STM-64 and STS-48/STM-16 applications.
  • 10 Gbit/s aggregate capacity. The framer can be configured to support:
    • One STS-192/STS-192c/STM-64/STM-64c stream.
    • Four STS-48/STS-48c/STM-16/STM-16c streams.
  • Supports one STS-192/STM-64 stream via a standard OIF SFI-4 interface (duplex 16-bit 622 MHz LVDS) for direct connection to SERDES and CRU/CSU devices.
  • Supports up to four STS-48/STM-16 via SFI-4 interfaces operating in nibble mode.
  • Provides working, protect, and APS interfaces for connection across system backplanes. Each interface consists of four ESSI (Extended SONET Serial Interface) CML links, operating at 2.488 Gbit/s.
  • Supports channelized (down to STS-1), concatenated, and arbitrarily concatenated (STS-3cxN) traffic. Changes in traffic configurations are automatically detected.
  • Terminates (or monitors) SONET/SDH Section, Line, and Path overhead and provides STS-1 granularity frame alignment and pointer processing.
  • Detects and inserts transport and path BIP-8 errors (B1, B2, B3). Detects signal degrade (SD) and signal fail (SF) threshold crossing alarms for B2 and B3.
  • Provides overhead passthrough for entire TOH, and re-mapping for B1, B2, and J0 bytes.
  • Provides dedicated pins to extract and reinsert the entire transport overhead.
  • Provides dedicated pins to extract section and line DCC.
  • Supports Automatic Protection Switching:
    • K1/K2 byte filtering and BER monitoring.
    • Direct line card APS connections via system side APS ports.
  • Supports centralized control of SONET/SDH processing by providing in-band status messaging (Transport, Path, and Equipment Status) on the ESSI ports.
  • Provides independent STS-1 Memory Switching Units (MSU) for combined time-slot interchange (TSI) and muxing functions in transmit and receive directions.
  • Provides independent STS-1 Memory Switching Units (MSU) at the DROP APS port for grooming traffic to support line card pairing or local traffic termination.
  • Provides line loopback from the line side receive streams to the transmit streams and supports diagnostic loopback on the system side interface.
GENERAL
  • General purpose 16-bit microprocessor interface for configuration, control and status monitoring.
  • Low power 1.2 V core with 2.5/3.3 V I/O.
  • Standard 5-signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.
  • 1292-pin FCBGA package.

Typical Applications include:

  • Multi Service Provisioning Platforms (MSPP).
  • Sub Wavelength Cross Connects.
  • Add/Drop Multiplexers.
  • DWDM Platforms.
  • Channelized Routers and Multi Service Switches.
  • Are you seeing all your results?

    If you are a PMC-Sierra Customer or Partner you may have permission
    to see additional results on the myPMC product page.
    Please log in to the myPMC product page to check.

    Product Brief
          Version Issue Date
      PDF Document PM5324 ARROW 1x192 SONET/SDH Transport Framer/Aggregator for OC-48 and OC-192 Product Brief [381 KB] PMC-2012473 3 2012-03-26
    Data Sheet
          Version Issue Date
    Locked PDF Document ARROW 1x192 ASSP Telecom Standard Product Data Sheet [1.85 MB] PMC-2032014 3 2005-03-15
    Application Note
          Version Issue Date
    Locked PDF Document Attaching Passive Heat Sinks to Organic Flip Chip Packages [142 KB] PMC-2020246 3 2007-05-02
    Locked Compressed Document Optimizing Pre-emphasis and Receive Equalization for Backplanes [493 kB] PMC-2021098 1 2002-10-31
    White Papers
          Version Issue Date
    Locked PDF Document An Introduction to Transport Networks for Telecommunications [384 KB] PMC-2050808 1 2005-07-20
    Locked PDF Document A Tutorial on SONET/SDH Automatic Protection Switching (APS) [353 KB] PMC-2050248 1 2005-02-15
    Locked PDF Document A Tutorial on SONET/SDH [819 KB] PMC-2030895 3 2005-03-23
    Locked PDF Document Application of Message Assisted Protection Switching (MAPS) to APS Architectures [402 KB] PMC-2021902 3 2003-09-22
    Sales Collateral
          Version Issue Date
    Locked PDF Document Notice of Change - All FCBGA Packages to be Standardized to the HDBU Substrate Package Outline [695 KB] PMC-2062178 1 2006-10-19
    Models
          Version Issue Date
    Locked Compressed Document FLOTHERM Detailed Model for PM5324 packaged in a 37.5 mm 1292 Pin FCBGA at assembler 'N' [3 KB] PMC-2042523 1 2004-12-14
    Symbols/Footprints
          Version Issue Date
    Locked Compressed Document PM5324-FI ARROW 1x192 1292 FCBGA CAD Symbols and Footprints [633 KB] PMC-2051177 1 2006-11-06
    Technical Overview
          Version Issue Date
    Locked PDF Document RASIO 3G for SONET/SDH Backplanes Technology Brief [64 kB] PMC-2030933 1 2003-05-29