Product Overview

Features

GENERAL

  • Single-chip multi-channel packet processor supporting a maximum aggregate bandwidth of 64 Mbit/s for line-rate throughput transfers of packet sizes from 40 to 9.6 Kbytes, for up to an aggregate of 32 T1s, 32 E1s or 1 DS-3.
  • Provides simultaneous support of PPP, Frame Relay, Multilink-PPP and Multilink-Frame Relay protocols. Alternative protocols supported via HDLC termination and full packet store of the data within the HDLC structure.
  • Supports two levels of priority queueing, with fragment interleaving, in the egress direction for single HDLC channels.
  • Typical Applications include:

    • Wireless Base Station Controllers or Radio Network Controllers.
    • Enterprise, Edge and Core Routers.
    • Multi-Service Edge aggreation equipment.
    • IETF PPP interfaces for routers.
    • Frame Relay interfaces for Multi-Service Switches.
    • FUNI or Frame Relay service interworking interfaces for ATM switches and multiplexers.
    • Internet/Intranet access equipment.
    • Multi-service DSLAM equipment.

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    Product Brief
          Version Issue Date
      PDF Document PM7307 FREEDM 32A1024LE Frame Engine and Datalink Manager Product Brief [268 KB] PMC-2050684 3 2006-03-22
    Data Sheet
          Version Issue Date
    Locked PDF Document FREEDM 32A1024LE Telecom Standard Product Data Sheet [1.33 MB] PMC-2051507 3 2006-08-04
    Application Note
          Version Issue Date
    Locked PDF Document Configuring SBI Compatible Devices [551 KB] PMC-2020180 6 2007-11-20
    Locked PDF Document FREEDM-336 Any-PHY Interface [747 kB] PMC-2010917 1 2001-07-20
    White Papers
          Version Issue Date
      PDF Document ATCA Design Considerations for Telecommunication Platforms [815 KB] PMC-2081221 1 2008-08-14